Hardware logic emulators are a powerful tool used during the design of integrated circuits such as application specific integrated circuits (known to those skilled in the art as "ASICs") and microprocessors. Hardware emulation systems allow a circuit designer to implement a logical equivalent of their design in hardware prior to implementing the design as an integrated circuit. This allows the user to determine whether their design performs as expected. It also allows for the co-design of related components such as software. Hardware emulators also allow users to verify that the circuit they have designed will function in the system in which the integrated circuit will eventually reside (i.e., the "target system"). Prior art emulators utilized reprogrammable logic integrated circuits that were interconnected together with programmable interconnect resources. For examples of such emulators, see U.S. Pat. Nos. 5,109,353, 5,036,473, 5,452,239, and, 5,475,830, all of which are assigned to the same assignee as the present invention and all of which are incorporated herein by reference.
Hardware logic emulation systems can also be constructed with many microprocessors interconnected in a massively parallel configuration. For an example of such an arrangement, see U.S. Pat. Nos. 4,306,286, 4,656,580, 4,914,612, and 5,551,013, all of which are incorporated herein by reference. In such an arrangement, the signals between each processor are time multiplexed. Thus, for each clock cycle, connections between the processors are established so that the processor resources necessary to evaluate the logical operations occurring during that clock cycle are interconnected. After the logic operations for that clock cycle are evaluated, the emulator reconfigures the interconnect between the processors so that the necessary processor resources are interconnected to evaluate the logical operations during the next clock cycle. U.S. Pat. No. 5,551,013, in particular, describes a preferred structure for implementation of the present invention.
Recently, latch-based designs have become common among integrated circuit designers because they can be implemented using smaller integrated circuit layout geometries than can other sequential logic functions such as flip-flops. However, while latch-based designs offer advantages when implemented on the integrated circuit, latches are difficult to implement in a processor-based emulation system. To understand why latches are difficult to implement in this environment, a brief discussion of flip-flops and latches will be provided. This discussion will refer to FIGS. 1-4. As is known to those of ordinary skill in the art, flip-flops are edge triggered sequential devices. Thus, upon the arrival of a clock ("CLK") edge, as shown in FIG. 2, the output ("Q") will take the value of the input ("D"). The flip-flop 10 shown in FIGS. 1-2 is a positive edge triggered flip-flop. In contrast to flip-flops, as is also known to those of ordinary skill in the art, latches are level sensitive sequential devices. Thus, in a latch, the output ("Q") follows the input ("D") when the clock ("CLK") goes high. The output ("Q") then holds that value when the clock ("CLK") goes low. The latch 20 shown in FIGS. 3-4 is a positive transparent latch.
A basic block diagram of the logic element of a presently preferred emulation processor is shown in FIG. 5a. The processors in a processor-based emulation system comprise an input stack 50, a logic table stack 60, and an output stack 70, as shown in FIG. 5a. The input stack 50 contains the input data signals that will comprise the inputs signals to the logic for a particular clock cycle. The output stack. 70 comprises the output signals from the logic evaluated during a particular clock cycle. The logic table stack 60 comprises the possible primitives that can be evaluated by the processor. Thus, for a given clock cycle, the input signals of the input stack are evaluated using the logic primitives of the logic table stack. The result of the evaluation is placed in the output stack.
In a typical integrated circuit design, a clock generation circuit 100 generates one or more clock signals from the clock signal which will be input to the integrated circuit design. A block diagram for a clock generation circuit 100 is shown in FIG. 5b. Clock generation circuit 100 takes the input clock signal FCLK (which can come from the target system) and generates one or more clock signals A and B. Clock signals A and B are synchronous clock signals. The clock generation circuit can further generate non-overlapping phases of clock A (signal Aph.sub.-- 1 and Aph.sub.-- 2) and clock B (signals Bph.sub.-- 1 and Bph.sub.-- 2). Clock signals that are non-overlapping never go high at the same time. In general, design engineers utilize non-overlapping clocks when designing multi-latch logic circuits. The reason for this is that when design engineers utilize overlapping clock signals in these circuit designs, it becomes difficult to control signal propagation through the latches in the user's design. This can lead to race conditions and unpredictable circuit behavior, both of which are undesirable.
The manner in which processor-based emulators operate are such that flip-flop based designs emulate properly. As discussed, processor-based emulation systems are cycle based. Thus, for a given datapath, the processor in which the particular evaluation is taking place levelizes the combinational logic, i.e., the processor orders the levels of combinational logic to ensure that the proper input signals to each level are present when that level of logic is evaluated. For each emulation cycle, the processor only evaluates the combinational logic between the sequential logic gates. In the case of a datapath containing flip-flops, such an arrangement results in functionally correct emulation because flip-flops are edge-sensitive. Therefore, the output of the flip-flop can only change state when an edge of the clock occurs. Thus, in a processor-based emulation system, for each clock cycle, the flip-flop only transfers the data signal from one datapath to the next. Thus, the flip-flops are inherently part of the datapath in a processor-based emulation system.
Latches, unlike flip-flops, are not inherently part of the design because of the transparent nature of a latch. As discussed, latches are level sensitive devices where the state of the output does not change until the clock signal it receives approaches the level that the latch is sensitive to. Because of this characteristic of latches, latches can be transparent. Transparency of a latch-based circuit path occurs when a series of latches in a particular circuit path are all clocked by the same clock phase. If a series of latches are clocked at the same time, the output signals of each of the datapaths pass right through the latches, i.e., the latches are transparent. When the possibility of transparency is present, the processor-based emulator will be unable to determine where the datapaths ends. This characteristic renders emulation of latch-based circuit designs problematic. Thus, in a processor based emulation system like that described in U.S. Pat. No. 5,551,013, emulation of latch-based designs can be unsatisfactory.
Just as in a flip-flop based design, a circuit path of a typical latch-based design contains a datapath comprised of combinational logic feeding the inputs to the latches. An example of such a circuit path 200 is shown in FIG. 6. The circuit path 200 of FIG. 6 is comprised of latch 210, the output Q of which feeds datapath 215. Datapath 215 feeds the input D of latch 220. The output Q of latch 220 feeds datapath 225, which feeds the input D of latch 230. The emulator wants to evaluate what the circuit 200 does to a data signal at the input D of latch 210 for one emulation cycle. This means the emulator evaluates the signal path from one sequential logic element to the next sequential element. However, if each of latches 210, 220 and 230 are clocked by the same clock signal (or the same phase of the same clock signal), when each of the latches 210, 220, 230 receive a clock edge, the latches will all be transparent at the same time. Because of this, the latches 210, 220, 230 will pass the signal on their inputs D directly to their outputs Q, i.e., the latches will be transparent. This transparency makes the emulator unable to evaluate what the circuit 200 did to the data signal through a single emulation cycle. For example, if latches 210 and 230 are clocked by the same clock signal (or the same phase of the same clock signal phi), and latch 220 is clocked by a different, non-overlapping clock signal (or a different phase of the same clock signal ph2), the latches are not transparent to each other. On the other hand, if latch 210 and latch 220 are clocked by the same clock signal (or the same phase of the same clock signal), and latch 230 is clocked by a different, non-overlapping clock signal (or a different, non-overlapping phase, of the same clock signal), latch 210 is transparent to latch 220. Latch 220, however, is not transparent to latch 230. The reason for this is that the input D to latch 220 depends on the output Q of the latch (not shown) preceding latch 210 because latch 220 is clocked by the same clock signal as latch 210 (latch 210 is transparent). In contrast, the value of the input D to latch 230 depends upon the output Q of latch 220 because latches 220 and 230 are clocked by different clock signals (i.e., latch 220 is not transparent).
In contrast, flip-flops cannot be transparent. Because of this, flip-flops become inherent in a cycle based emulation environment, i.e., the output of datapath 215 and datapath 225 will be stored in flip-flops 220 and 230 respectfully. This property of flip-flops makes them ideal for this type of emulation environment. On the other hand, the transparency of latches makes them difficult to emulate. While it is possible to just substitute flip-flops for the latches in the user's design and over-sampling the signal that is input to the flip-flops to obtain the desired transparency effect, such a method results in significantly slower emulation speeds. Reduced emulation speed is highly undesirable. Thus a method of optimizing latch-based design for emulation in a processor-based emulation system is needed.